DLLSEL=DLLSEL_0, BTO=BTO_0, WPOL1=WPOL1_0, WPOL0=WPOL0_0, DQSMD=DQSMD_0, DQSSEL=DQSSEL_0, MDIS=MDIS_0
Module Control Register
| SWRST | Software Reset |
| MDIS | Module Disable 0 (MDIS_0): Module enabled 1 (MDIS_1): Module disabled. |
| DQSMD | DQS (read strobe) mode 0 (DQSMD_0): Dummy read strobe loopbacked internally 1 (DQSMD_1): Dummy read strobe loopbacked from DQS pad or DLL delay chain. Details information at descriptions of DQSSEL bit. |
| WPOL0 | WAIT/RDY# polarity for NOR/PSRAM 0 (WPOL0_0): Low active 1 (WPOL0_1): High active |
| WPOL1 | WAIT/RDY# polarity for NAND 0 (WPOL1_0): Low active 1 (WPOL1_1): High active |
| DQSSEL | Select DQS source when DQSMD and DLLSEL both set. 0 (DQSSEL_0): SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode. 1 (DQSSEL_1): SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode. |
| DLLSEL | Select DLL delay chain clock input. 0 (DLLSEL_0): DLL delay chain clock input is from NAND device’s DQS pad. For NAND synchronous mode only. 1 (DLLSEL_1): DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only. |
| CTO | Command Execution timeout cycles |
| BTO | Bus timeout cycles 0 (BTO_0): 255*1 1 (BTO_1): 2552 - 2552^30 2 (BTO_2): 2552 - 2552^30 3 (BTO_3): 2552 - 2552^30 4 (BTO_4): 2552 - 2552^30 5 (BTO_5): 2552 - 2552^30 6 (BTO_6): 2552 - 2552^30 7 (BTO_7): 2552 - 2552^30 8 (BTO_8): 2552 - 2552^30 9 (BTO_9): 2552 - 2552^30 31 (BTO_31): 255*2^31 |